gated clock implementation using altera standard scheme

I believe the problem is that you did not negate the clock input to the register.

Your always statement should be:

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always @(negedge CLK)

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remove the (or cken)

If you right click on the warning message and click "Help" you get some useful info:

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If the combinational logic uses an AND gate, the clock port of the register that drives the AND gate should be active on the falling edge and the clock port of the register driven by the AND gate should be active on the rising edge.

or

If the combinational logic uses an OR gate, the clock port of the register that drives the OR gate should be active on the rising edge and the clock port of the register driven by the OR gate should be active on the falling edge.

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Jake