Gated clock conversion and state machines

What do you mean by 'gated clock tree'?

I have run state machines at an effective lower frequency than the master clock by using an enable signal for the state machine.

Ie, something like this:

reg [3:0] count = 0;
reg [3:0] state = 0;
reg enable = 0;

always @(posedge clk)
    begin
    count <= count+1;
    enable <= (count == 0);
    end

always @(posedge clk)
    begin
    if (reset)
        state <= 0;
    else
        if (enable)
            begin
            case (state)
            0: state <= 1;
            1: state <= 2;
            ...
            default: state <= 0;
            end
    end

so that in this case the state machine triggers every 16 clocks based on the value in count.

My problem is related to gated clock conversion to clock enable. By gated clock tree I meant all the logic which is clocked by gated clock.

Well I am not sure what you mean by a 'gated clock' then. Can you provide a simple example of your logic in verilog?

To me, a 'gated clock' means inserting logic in a clock signal path to control the usage of the clock.

That is not a recommended design practice for FPGAs. Better to distribute a common clock and use enable signals on registers.

You may checkout the Clock-Gating Methods below, see if it meet your design requirement :

https://www.intel.com/content/www/us/en/docs/programmable/683082/21-3/recommended-clock-gating-methods.html

Since there are no feedback for this thread, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best Regards,

Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos and select the best solution.