Gated clock conversion and state machines

What do you mean by 'gated clock tree'?

I have run state machines at an effective lower frequency than the master clock by using an enable signal for the state machine.

Ie, something like this:

reg [3:0] count = 0;
reg [3:0] state = 0;
reg enable = 0;

always @(posedge clk)
    begin
    count <= count+1;
    enable <= (count == 0);
    end

always @(posedge clk)
    begin
    if (reset)
        state <= 0;
    else
        if (enable)
            begin
            case (state)
            0: state <= 1;
            1: state <= 2;
            ...
            default: state <= 0;
            end
    end

so that in this case the state machine triggers every 16 clocks based on the value in count.