Forum Discussion
robert_g
New Contributor
New ContributorGated clock conversion and state machines
I'm having issues with gated clock conversion if there is state machine in gated clock tree. As soon as I remove fsm or select synthesis option to not infer state machines the gated clock conversion ...
ak6dn
Regular Contributor
Regular ContributorWell I am not sure what you mean by a 'gated clock' then. Can you provide a simple example of your logic in verilog?
To me, a 'gated clock' means inserting logic in a clock signal path to control the usage of the clock.
That is not a recommended design practice for FPGAs. Better to distribute a common clock and use enable signals on registers.
