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ak6dn
Regular Contributor
3 years agoWell I am not sure what you mean by a 'gated clock' then. Can you provide a simple example of your logic in verilog?
To me, a 'gated clock' means inserting logic in a clock signal path to control the usage of the clock.
That is not a recommended design practice for FPGAs. Better to distribute a common clock and use enable signals on registers.