robert_gNew Contributor3 years agoGated clock conversion and state machines I'm having issues with gated clock conversion if there is state machine in gated clock tree. As soon as I remove fsm or select synthesis option to not infer state machines the gated clock conversion ...Show More
RichardT_alteraSuper Contributor3 years agoYou may checkout the Clock-Gating Methods below, see if it meet your design requirement : https://www.intel.com/content/www/us/en/docs/programmable/683082/21-3/recommended-clock-gating-methods.html
Recent DiscussionsRequest for Quartus encryption licenseRegarding the issue of UFM not startingTiming analysis - long combinational pathtiming violation fixThe quartus license works with version 25.0 but not with version 17.0