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Altera_Forum's avatar
Altera_Forum
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10 years ago

Functions, Procedures, Packages, TextIO, and Sign Magnitude Math

Hello,

I need to create a package containing 3 functions and a procedure that will compute the addition, subtraction, multiplication, and division of two signed magnitude binary numbers respectfully. The operands can take any arbitrary length (Some_Value downto 0). I also have to create a text file with the inputs and their corresponding sum, difference, product, and quotient/remainder.

I was able to get the addition, subtraction, and multiplication functions to work for a set length value, but I'm having trouble finishing the divide procedure. I'm also not quite sure how to adjust the code to account for the arbitrary input length, or how to get start on the TextIO part.

Any help you can give me will be greatly appreciated!

Thanks,

Mitch

The following are the software and hardware I have been using:

  1. Quartus II 13.1

  2. ModelSim 10.2c

  3. Cyclone IV E - EP4CE115F29C7

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    What a complete failure of a lab exercise. First of all, this is about the worst thing to do with VHDL:

    type SIGN_MAG is array (natural range <>) of std_logic;

    The std_logic_vector, unsigned and signed types already do this, so why declare another type and make your life harder? Please provide this as feedback to the lab.

    Clearly what this terrible lab is trying to get you to do is build your own multiplier and own divider (forcing you do to some research). The only problem is that building them via a procedure is only going to give you a poorly optimised circuit as it wont have any pipelining in. The maximum frequency will be very slow, and slower the wider the operands are.

    So, what have you done so far?