Honored Contributor
Honored ContributorWhat a complete failure of a lab exercise. First of all, this is about the worst thing to do with VHDL:
type SIGN_MAG is array (natural range <>) of std_logic; The std_logic_vector, unsigned and signed types already do this, so why declare another type and make your life harder? Please provide this as feedback to the lab. Clearly what this terrible lab is trying to get you to do is build your own multiplier and own divider (forcing you do to some research). The only problem is that building them via a procedure is only going to give you a poorly optimised circuit as it wont have any pipelining in. The maximum frequency will be very slow, and slower the wider the operands are. So, what have you done so far?
