Functional Simulation is Correct,But Timing is Incorrect

Hi, alterwoord... I'm sorry, I try to simulate a simple wimedia LDPC coder-encoder chain.. I give all requested signals (Clk,Reset,in_valid,start and end of packet pulses, etc) to the encoder but the outputs remains in absolute undefined status on all the signals.. do you meet similar issue when you simulate? (quartus+modelsim, no errors) . )'m perform a simulation with a 100 mhz pll clk.. conder and encoder are in chain with common avalon signals for interconnections