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Altera_Forum's avatar
Altera_Forum
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13 years ago

frequency to voltage converter

Hey everyone,

I wrote a frequency to voltage converter and implementing it on a Altera Cyclone FPGA board( with an 64Mhz internal clock)

It works perfectly until it reaches 32 Mhz, at 32 Mhz it starts to countdown( decreasing instead of increasing)

Can someone please explain this weird thing?

module measure(

input wire signed [11:0] in,

input clk,

output wire signed [13:0] f

);

reg [15:0] in_count;

reg [15:0] out_count;

reg [15:0] clk_count;

reg clk_complete;

initial

begin

in_count=16'b0000000000000000;

out_count=16'b0000000000000000;

clk_count=16'b0000000000000000;

clk_complete=1'b0;

end

assign f[13:0]=({1'b0,out_count[15:5]});

always @(posedge clk)

begin

clk_count=clk_count+16'b0000000000000001;

clk_complete=1'b0;

if (clk_count==16'b1111111111111111)

begin

out_count<=in_count;

clk_count<=16'b0000000000000000;

clk_complete<=1'b1;

end

end

always@ (posedge clk_complete or posedge in[11])

begin

if (clk_complete==1'b1)

begin

in_count<=16'b0000000000000000;

end

else

begin

in_count<=in_count+16'b0000000000000001;

end

end

endmodule

Thanks in advance

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Don't use a signal as clock, this brings up timing errors. Try to make the complete logic work synchronously inside the always @(posedge clk) block.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    This is definetly not the isue here. It works perfectly until it gets to 32mhz then it works well too but it goes backwards.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Suggestion: next time wrap your code using the# button for the forum so the spacing is preserved.

    Just looking at the code, I do see one problem. Assuming in[11] is an asynchronous clock when compared to clk, the assignment of in_count to out_count is unstable. I suggest trying to search for information regarding crossing clock domains.

    I also can't say that I'm thrilled with the double use of posedge in your second process. If in[] is an internally registered signal, I also agree with FvM that doing this can cause timing issues with Timequest (unless you setup your SDC correctly).
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    This is definetly not the isue here. It works perfectly until it gets to 32mhz then it works well too but it goes backwards.

    --- Quote End ---

    In other words, you have a problem that you don't understand, but you know pretty well what's not the cause.

    Why are you asking at all?

    --- Quote Start ---

    doing this can cause timing issues with Timequest (unless you setup your SDC correctly).

    --- Quote End ---

    Timing constraints can possibly extend the applicable frequency range, but don't turn a bad construct into a good one.