Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

frequency to voltage converter

Hey everyone, I wrote a frequency to voltage converter and implementing it on a Altera Cyclone FPGA board( with an 64Mhz internal clock) It works perfectly until it reaches 32 Mhz, at 32 Mhz it ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Suggestion: next time wrap your code using the# button for the forum so the spacing is preserved.

Just looking at the code, I do see one problem. Assuming in[11] is an asynchronous clock when compared to clk, the assignment of in_count to out_count is unstable. I suggest trying to search for information regarding crossing clock domains.

I also can't say that I'm thrilled with the double use of posedge in your second process. If in[] is an internally registered signal, I also agree with FvM that doing this can cause timing issues with Timequest (unless you setup your SDC correctly).