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Altera_Forum's avatar
Altera_Forum
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8 years ago

frequency meter on cyclone IV E ,without display frequency

hi everybody.

sorry for my english.

I ask for your help for released an simple frequency meter with vhdl (i am newbie on FPGA):

https://alteraforum.com/forum/attachment.php?attachmentid=14027&stc=1

Input

"ref_clock" is 50 MHz periode 20ns of cyclone IV E.

"signal" is mesured signal from encoder

Output

cycle of test errors every 1 sec

if frequency >= 1000 Hz ==>error1 = 1 //1 is logic HIGH

if frequency >= 2000 Hz ==> error1 = 1 and error2 = 1

else error1 = 0 and error2 = 0 //0 is logic LOW

thank you.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    thank you Tricky, josyb.

    Tricky, how to do it in the simplest way possible.

    josyb, I didn't understand half of the code.

    I told you that I was newbie in(FPGA VHDL...)

    Here is my code 

    
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity freq_meter is
port (
  i_ref_clock    : in  std_logic; -- 50 MHz
  i_signal       : in  std_logic; -- from encoder
  o_error1       : out std_logic; 
  o_error2       : out std_logic);
end freq_meter;
architecture freq_meter_arch of freq_meter is
begin
--  CLOCK REFERENCE domain
variable clock_secand_decounter : integer := 50000000;
variable i_signal_counter : integer := 0;
if(clock_secand_decounter<=1) then
	if(rising_edge(i_signal)) then
		i_signal_counter <=i_signal_counter+1;
  		if(rising_edge(i_ref_clock)) then
			clock_secand_decounter <= clock_sec_dec -1;
		end if;
	end if;
end if;
if(clock_secand_decounter >= 1000)then
	o_error1='1';
	o_error2='0';
	elsif(clock_secand_decounter >= 2000)then
	o_error1='1';
	o_error2='1';
else
	o_error1='0';
	o_error2='0';
end if;
end freq_meter_arch;

    Yes I know there is a lot of errors

    Here is the timeline.

    https://www.alteraforum.com/forum/attachment.php?attachmentid=14030
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    The syntax errors should be easy enough for you to fix by referencing a vhdl text book.

    But there are more fundamental errors - eg. Having a rising edge inside a rising edge will never occur in reality. I suggest you work through a tutorial that covers basic logic to try and understand what is wrong with your code.