frequency meter on cyclone IV E ,without display frequency

thank you Tricky, josyb.

Tricky, how to do it in the simplest way possible.

josyb, I didn't understand half of the code.

I told you that I was newbie in(FPGA VHDL...)

Here is my code

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity freq_meter is
port (
  i_ref_clock    : in  std_logic; -- 50 MHz
  i_signal       : in  std_logic; -- from encoder
  o_error1       : out std_logic; 
  o_error2       : out std_logic);
end freq_meter;
architecture freq_meter_arch of freq_meter is
begin
--  CLOCK REFERENCE domain
variable clock_secand_decounter : integer := 50000000;
variable i_signal_counter : integer := 0;
if(clock_secand_decounter<=1) then
	if(rising_edge(i_signal)) then
		i_signal_counter <=i_signal_counter+1;
  		if(rising_edge(i_ref_clock)) then
			clock_secand_decounter <= clock_sec_dec -1;
		end if;
	end if;
end if;
if(clock_secand_decounter >= 1000)then
	o_error1='1';
	o_error2='0';
	elsif(clock_secand_decounter >= 2000)then
	o_error1='1';
	o_error2='1';
else
	o_error1='0';
	o_error2='0';
end if;
end freq_meter_arch;

Yes I know there is a lot of errors

Here is the timeline.

https://www.alteraforum.com/forum/attachment.php?attachmentid=14030