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Altera_Forum's avatar
Altera_Forum
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14 years ago

FPGA visual design tool, very tiny

http://robei.com/wordpress/wp-content/uploads/2011/06/struct-1024x821.jpg

It has the following advantages comparing with other hardware design products.

1. Simple user interface, easy to learn and easy to use. Compare with other tools, our software can let you manage it in 15 minutes.

2. Based on most popular open source platform -QT, which is also known as cross platform SDK, so it has the potential to work on Windows, Linux and Mac plus some embedded platforms.

3. Integrating with most famous Icarus Verilog compiler(version 0.9.3, you can download here), it support both behavior level and RTL level verilog simulation.

4. It has a waveform viewer to visualize the simulation result.

5. It can help developer to find connection errors before going to code level. Let developer focus on algorithms instead of manage coding.

6. It supports both Bottom-up and Top-down design methodology.

7. It supports command line action script, which means designer can use commands to design their system.

8. It allows designer to change or type in data like editing properties.

9. Modern user interface, works fast without any delay.

10. Very tiny, requires very little memory(<100M) to run.

11. The current version only support simulation, but you can use the generated verilog code to work with Xilinx ISE.

12. Multiple language support.

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    This tool targeting to entry level and would be a great education tool.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    This software has a new version which completely free for personal, education, research use. The newest version only 5.0Mbits, which is much smaller than 1.0 version.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    I think I already commented on your work in the german fpga forum, I think. For me this is a nice a approach to design small circuits with, but for larger designs, we need more than 2D-interfaces and hardware related entry know from the PCB design.

    Especially nowadays's designs are set up by mathematical approaches defining values, streams, reg banks and such thinks, which are not sticking anymore to bit related data entry. (most of that is ready anyway and things are placed by dropping in VHDL modules or ready built cores from vendors).

    So I do not need a physical buffer, but a logical one, like the data fields in SW or MATLAB's arrays.

    I do not need a bit based input or compare, but a representation of a mathematical equation inckluding sizing, limiting, offset shifting and rounding

    I am doing this with ready built excel blocks offering that all by just copy and past. The can even tweek the bits down to the requiered resolution automatically analyzing the range field and the input values at the "engineering level" ( calculation SNR, precision, accuracy) and setting the appriate values. Doing this this way. I have the comple min/max calculation of the data ready visible in excel and so to speak a complete documentation of the functional behaviour of the circuit part. My Excel building block produces native VHDL lines, working everywhere, fully simulated, portable and tested for years.

    I found nothing similar and quicker, neither with "HDL Author", nor "HDL Designer", nor "System Generator" and Simulink Blockset. All of that is physical entry only and not functional entry, but physics or at least proposals for the physics should be the the results of a design process.