Honored Contributor
Honored ContributorI think I already commented on your work in the german fpga forum, I think. For me this is a nice a approach to design small circuits with, but for larger designs, we need more than 2D-interfaces and hardware related entry know from the PCB design.
Especially nowadays's designs are set up by mathematical approaches defining values, streams, reg banks and such thinks, which are not sticking anymore to bit related data entry. (most of that is ready anyway and things are placed by dropping in VHDL modules or ready built cores from vendors). So I do not need a physical buffer, but a logical one, like the data fields in SW or MATLAB's arrays. I do not need a bit based input or compare, but a representation of a mathematical equation inckluding sizing, limiting, offset shifting and rounding I am doing this with ready built excel blocks offering that all by just copy and past. The can even tweek the bits down to the requiered resolution automatically analyzing the range field and the input values at the "engineering level" ( calculation SNR, precision, accuracy) and setting the appriate values. Doing this this way. I have the comple min/max calculation of the data ready visible in excel and so to speak a complete documentation of the functional behaviour of the circuit part. My Excel building block produces native VHDL lines, working everywhere, fully simulated, portable and tested for years. I found nothing similar and quicker, neither with "HDL Author", nor "HDL Designer", nor "System Generator" and Simulink Blockset. All of that is physical entry only and not functional entry, but physics or at least proposals for the physics should be the the results of a design process.
