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RMees's avatar
RMees
Icon for New Contributor rankNew Contributor
8 years ago

FPGA IP Evaluation Mode when using a remote JTAG server.

My design contains a SerialLite III IP, but I dont have the required license. The FPGA image that is produced is a "time_limited" version. I run my FPGA tools on a cloud based Linux machine. The F...
Nooraini_Y_Intel's avatar
Nooraini_Y_Intel
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Hi RMees,

Apologize for long delay as I'm still finding the right engineer here that can help on this Serial Lite III Evaluation IP mode. As far I manage to test a simple time_limited .sof file using a different Evaluation IP from a remote host which indicate that when using remote JTAG server to load the FPGA board is in Tethered mode. in the project design, the OCP time out signal was set to active_high. After programming the time_limited .sof file from a remote host/machine, the Quartus programmer will prompt a small window showing the remaining time before expire. When running the SingnalTap I can observe the OCP ip_timeout singal is low which indicate the Evaluation IP has not yet expire.

Regards,

Nooraini