Honored ContributorHi,
When I run my code in emulator mode, the result is right. But after compile and run it in FPGA, it blocked! My code have used a lot of channels. What's the problem? How to debug it? Thanks!
Honored Contributor"When I run my code in emulator mode" - emulator mode? Do you mean in a simulation? (simulation is not emulation!)
"it blocked!" - Care to elaborate? "My code have used a lot of channels." - Channels of what? "What's the problem?" - There is absolutely no way of us knowing. You haven't given us any code, warnings, error messages, anything. "How to debug it?" - SignalTap could be useful. Check also for any warnings and fix them. Look through the RTL viewer and check all looks accurate. Probe any clock and input signals to your FPGA to make sure they are correct.Honored ContributorPlease, provide a better question. Saying "my FPGA wont work, what is wrong" does not help us to help you.
What are you doing? Can you post some code? are you simulating? can you post the test bench?Honored ContributorBest way is posting a minimal code that makes "it blocked!".
Reduce your example from unimportant parts. May be, you same in progress of reducing without assistance understand a cause of problem. Or if increase amount of channels, then in model you may see hangs. Verification is absolute fixed process, and in FPGA may be flexible vibrations and inconstancy, nonrepeatings bahaviour. View similar thread https://www.alteraforum.com/forum/showthread.php?t=56402.Honored ContributorDeadlocks that do not show up in emulation but happen during execution on the board are pretty much always caused by channel ordering issues. Unless you use channel fences, the compiler can and will reorder your channels to improve pipeline performance/efficiency, which could cause deadlocks. Use channel fences to fix the order of channel operations in your kernel.
