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Altera_Forum's avatar
Altera_Forum
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8 years ago

FPGA code is blocked

Hi, When I run my code in emulator mode, the result is right. But after compile and run it in FPGA, it blocked! My code have used a lot of channels. What's the problem? How to debug ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Best way is posting a minimal code that makes "it blocked!".

Reduce your example from unimportant parts.

May be, you same in progress of reducing without assistance understand a cause of problem.

Or if increase amount of channels, then in model you may see hangs.

Verification is absolute fixed process, and in FPGA may be flexible vibrations and inconstancy, nonrepeatings bahaviour.

View similar thread https://www.alteraforum.com/forum/showthread.php?t=56402.