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Altera_Forum
Honored Contributor
8 years agoAs you can see from the diagram.
Task 1: FPGA performs low-level and parallel interface functions for external components. Task 2: First-In First-Out (FIFO) for communication with the DSP. Question: How to define the external components in my VHDL program? Question: In which part of the program do i include the FIFO. Note: i'm sorry in advance in case my questions are very annoying. I'm really new to this.