Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Found pins functioning as undefined clocks and/or memory enables

After performing a Classical Timing Analysis, I got the following warning from Quartus II v 7.2:

"Found pins functioning as undefined clocks and/or memory enables"

I've created the clock for the node specified as undefined clock, then run the Timing Analyzer again. The warning are still there. Does anyone know how to define a clock?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    I believe this happens if for example you are using an external clock, you need to tell Quartus timing analiser that the signal is a clock: go into assignments - Timing Analisys Settings; click on Individual Clocks and select New. Type a name for the input and select the node, the required fmax I guess is the maximum frequency of that clock. By doing this the timing analisys will check if the circuit can run a t that frequency. Hope this helps.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    --- Quote Start ---

    After performing a Classical Timing Analysis, I got the following warning from Quartus II v 7.2:

    "Found pins functioning as undefined clocks and/or memory enables"

    I've created the clock for the node specified as undefined clock, then run the Timing Analyzer again. The warning are still there. Does anyone know how to define a clock?

    --- Quote End ---

    Hmm, you say you have defined the node specified as undefined clock, can you shows your create clock TCL settings and the original message of the warning message so that we can check for you? I need to know whether you set the clock correctly or not.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    --- Quote Start ---

    I believe this happens if for example you are using an external clock...

    --- Quote End ---

    From my experience people always remember to set the external clock (if he knows that he uses such pin as clock) but forget about the implicit generated signal (as node in design) that is used to drive other register in an "always @ block" inferred by the synthesis tool as clock port of the register.

    Check you design to see whether you are intended to use such generated signal as clock or you just accidentally do so, it might be not your intention.