Forum Discussion
Altera_Forum
Honored Contributor
18 years ago --- Quote Start --- I believe this happens if for example you are using an external clock... --- Quote End --- From my experience people always remember to set the external clock (if he knows that he uses such pin as clock) but forget about the implicit generated signal (as node in design) that is used to drive other register in an "always @ block" inferred by the synthesis tool as clock port of the register. Check you design to see whether you are intended to use such generated signal as clock or you just accidentally do so, it might be not your intention.