Forcing signal for Analyze & Compile at partition boundary

Hi Rysc,

Thanks for the speedy reply! Yes, this is what I'm doing above the top level partition. (Similar to the solution of inserting a dummy PLL to get the clocking right shown in the Quartus manual.)

Unfortunately as this is at a lower level of the design (the FPU) and I would have to insert this passthrough module as a sort of 'shim' between the instantiating and sub-partition IP. It would certainly work, but I'd still end up changing the code (if only the instantiation).

As I think that code modification is inevitable I will probably do:

`if FPGA
`define CPU_SCANENABLE 1'b0
`else
`define CPU_SCANENABLE scanenable
`endif

in the header file and substitute scanenable in the RTL for `cpu_scanenable

If there is a 'new feature' list for Quartus, this would be a useful addition as I know I've bumped into similar issues before (on a competing synthesis tool!)

Regards,

++Simon