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Altera_Forum
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13 years ago

Forcing signal for Analyze & Compile at partition boundary

Does anyone know if it is possible to 'force' a signal to 0 on a lower level design partition boundary for synthesis? The normal way would be to just change the RTL code, possibly with an `ifde...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Add a level of hierarchy that just instantiates the IP, passes all signals through as normal, but puts '0' in that pin. (An assignment would be easier, but that's the recommended way)