Altera_Forum
Honored Contributor
18 years agoforce quartus to instantiate LPM_COUNTER from HDL
Dear All,
is there any way how to force quartus to instantiate LPM_COUNTER when I describe counter in VHDL?? I have following structure: process (CLK, RESETNA) is begin -- process if RESETNA = '0' then -- asynchronous reset (active low) ItemCount <= (others => '0'); elsif CLK'event and CLK = '1' then -- rising clock edge -- synchronous load: if ItemCountClear = '1' then -- load data ItemCount <= (others => '0'); elsif ItemCountEnable = '1' then ItemCount <= ItemCount - '1'; end if; end if; end process; Whatever I do with this structure (using variables instead of signals, changing the position of ifs, increase instead of decrease etcetc), the result is always register + ADDER + BUNCH OF MULTIPLEXERS. Why that? What I want is either LPM_COUNTER, or series of registers + some glue logic. Is there any way how to force it? thx d.