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... one would expect that LPM implementation gives better results.
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That's not necessarily true.
The QII 7.2 project in counters_qii7.2.zip contains your RTL counter and instantiates the equivalent lpm_counter. Both counters are configured as 64 bits. The project uses the default Quartus settings for Analysis & Synthesis and the Fitter.
There is no difference in resource utilization. Each counter uses 65 logic cells including 64 registers.
There is only a tiny difference in performance, and that might be because of what the Fitter by chance chose to do differently for the two counters. The LPM version is only 0.114 ns faster than the RTL version in an EP3C5F256C6.
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I have found that here:
http://www.altera.com.cn/support/examples/vhdl/vhd-counter-synch.html they claim that this inferres LPM_COUNTER. However when added into my project, it generates register + adder + multiplexer.
so this behavior sounds to me rather like a bug.
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The readme file on that page has this:
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Software Tool Requirements
==========================
The Quartus II software version 4.0 or later, or the Mentor Graphics
Precision RTL Synthesis 2003, or Synplicity Synplify Pro 7.3.3.
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I compiled the same design with QII 4.0. (I changed to an older device so that I could use that version.) The results are in counters_qii4.0.zip. As you can see from the Analysis & Synthesis Resource Utilization by Entity and Fitter Resource Utilization by Entity tables in the report files, lpm_counter was inferred for the RTL counter.
Apparently Quartus integrated synthesis has been changed since version 4.0 not to infer lpm_counter because the results are just as good without lpm_counter.
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