for generate

You have the process inside the generate, so the process will be generated several times. i_data, s and i are driven 4 times - you cannot do this.

Move the process outside of the generate.

Like this :

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity cdma_testbipo is

generic (

longueur : natural :=4 );

port (

clk : in std_logic ;

rst : in std_logic ;

data: in std_logic ;

odata: out std_logic ;

isis :out integer range 0 to longueur-1 ;

CD :in std_logic_vector( (4*longueur)-1 downto 0) ;

S :out integer range -8 to 7 );

end entity ;

architecture beh of cdma_testbipo is

type RAM is array (0 to longueur-1) of integer range -8 to 7;

signal i :integer range 0 to longueur-1 ;

signal code : RAM;

signal idata :std_logic ;

begin

F:for j in 0 to (4*longueur)-1 generate

begin

code(j)<=to_integer(signed(CD((4*longueur)-1 downto 3*longueur)));

code(j)<=to_integer(signed(CD((3*longueur)-1 downto 2*longueur))) ;

code(j)<=to_integer(signed(CD((2*longueur)-1 downto longueur )));

code(j)<=to_integer(signed(CD(longueur-1 downto 0))) ;

bpsk :process(clk,rst)

begin

if(rst='1')then

i<= 0;

else

if(clk'event and clk='1')then

i<=i+1 ;

if(idata='0') then

s<=-code(i);

else

s<=code(i);

end if;

if(i=longueur-1) then

idata<=data;

end if;

end if ;

end if ;

end process ;

isis<=i;

odata<=idata ;

end generate F ;

end architecture ;

Error : Error (10384): VHDL assignment error at cdma_testbipo.vhd(34): index 4 is outside the range (0 to 3) of object "code"

How can you correct this erreor ! plz

or like this :

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity cdma_testbipo is

generic (

longueur : natural :=4 );

port (

clk : in std_logic ;

rst : in std_logic ;

data: in std_logic ;

odata: out std_logic ;

isis :out integer range 0 to longueur-1 ;

CD :in std_logic_vector( (4*longueur)-1 downto 0) ;

S :out integer range -8 to 7 );

end entity ;

architecture beh of cdma_testbipo is

type RAM is array (0 to longueur-1) of integer range -8 to 7;

signal i :integer range 0 to longueur-1 ;

signal code : RAM;

signal idata :std_logic ;

begin

bpsk :process(clk,rst)

begin

F:for j in 0 to (4*longueur)-1 generate

begin

code(j)<=to_integer(signed(CD((4*longueur)-1 downto 3*longueur)));

code(j)<=to_integer(signed(CD((3*longueur)-1 downto 2*longueur))) ;

code(j)<=to_integer(signed(CD((2*longueur)-1 downto longueur )));

code(j)<=to_integer(signed(CD(longueur-1 downto 0))) ;

if(rst='1')then

i<= 0;

else

if(clk'event and clk='1')then

i<=i+1 ;

if(idata='0') then

s<=-code(i);

else

s<=code(i);

end if;

if(i=longueur-1) then

idata<=data;

end if;

end if ;

end if ;

end generate F ;

end process ;

isis<=i;

odata<=idata ;

end architecture ;

Like this :

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity cdma_testbipo is

generic (

longueur : natural :=4 );

port (

clk : in std_logic ;

rst : in std_logic ;

data: in std_logic ;

odata: out std_logic ;

isis :out integer range 0 to longueur-1 ;

CD :in std_logic_vector( (4*longueur)-1 downto 0) ;

S :out integer range -8 to 7 );

end entity ;

architecture beh of cdma_testbipo is

type RAM is array (0 to longueur-1) of integer range -8 to 7;

signal i :integer range 0 to longueur-1 ;

signal code : RAM;

signal idata :std_logic ;

begin

F:for j in 0 to (4*longueur) generate

begin

code(j)<=to_integer(signed(CD((4*longueur)-1 downto 3*longueur)));

code(j)<=to_integer(signed(CD((3*longueur)-1 downto 2*longueur))) ;

code(j)<=to_integer(signed(CD((2*longueur)-1 downto longueur )));

code(j)<=to_integer(signed(CD(longueur-1 downto 0))) ;

bpsk :process(clk,rst)

begin

if(rst='1')then

i<= 0;

else

if(clk'event and clk='1')then

i<=i+1 ;

if(idata='0') then

s<=-code(i);

else

s<=code(i);

end if;

if(i=longueur-1) then

idata<=data;

end if;

end if ;

end if ;

end process ;

isis<=i;

odata<=idata ;

end generate F ;

end architecture ;

You can modify My programm if it's possible !

Thank you !

But if I did, how will you learn?

I told you what the problem was... you put 4* in the generate, so you either need to make the code signal 4* wider or go back to the origional version.

The code looks like a different but not lesser erroneous version of previously posted stuff. http://www.alteraforum.com/forum/showthread.php?t=45040

To mention just an arbitrary detail, you have four consecutive assignments to code(j), doing this outside a process causes a "multiple driver error". I'm under the impression that you don't know what you want to achieve at all, unfortunately me neither. I see that you are splitting input vector CD into four 4-bit signed numbers, respectively integers. But only one can be assigned to an element of array code at a time.

My suggestion, sketck the intended data flow on a piece of paper before writing VHDL.