for generate

The code looks like a different but not lesser erroneous version of previously posted stuff. http://www.alteraforum.com/forum/showthread.php?t=45040

To mention just an arbitrary detail, you have four consecutive assignments to code(j), doing this outside a process causes a "multiple driver error". I'm under the impression that you don't know what you want to achieve at all, unfortunately me neither. I see that you are splitting input vector CD into four 4-bit signed numbers, respectively integers. But only one can be assigned to an element of array code at a time.

My suggestion, sketck the intended data flow on a piece of paper before writing VHDL.