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Altera_Forum
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14 years ago

Floating point multiplication megafunction

Hello everyone,

I am currently trying to use floating point multiplication megafunction. But I always get result 0 no matter what are the inputs.

This is what I do:

1. Get into megawizard and choose to generate verilog file

2. define floating point format as "Single extended precision(43 to 64 bits)

3. define dataa, datab and result widths as 45 bits

4. define exponent width as 13 bits

5. define output latency to be 11

6. choose to generate verilog file and symbol file

7. click finish

For the input data I use concatenation method to fit the width of dataa and datab(that were defined in step 3).

My dataa is a constant which is 0.172212 in decimal and then I convert it using fraction binary method as mantissa bit. Then I use concatenation method to insert the sign bits(0 because positive) and exponent width(13'b0) into the mantissa bit. It become 1 bit sign, 13 bits exponent bits and 31 bit mantissa.

My datab is not a constant and I use also concatenation method to fit the width of the megafuntion.

After I do that, no matter what I always get 0 at result.

After that I thought may be I should use the clk_en port at the megafunction. Then I add clk_en port and feed it with high signal. But the result is still 0.

What should I do everyone to get a correct result?

Thank you in advanced for your guidance:D

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  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    with your required range, have you considered using fixed point? then its just integer arithmatic and much less resource usage than floating point.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Thank you kaz for your explanation. Now I understand what consideration to make when deciding the output latency. but the problem is we cannot have the latency of the megafunction as "our own will". For example the output latency for megafunction ALTFP_DIV are only 6, 14, 33. How if we want 50 output latency? All this time I always generate a slower clock to match the output latency or the timing diagram between each component.

    What do you think kaz? Thanks in advance kaz.

    Thank you Tricky.

    Actually I thought of using fixed point but I cannot find any megafunction for fixed point (at arithmetic part). What I found is anything with ALTFP initial which is for floating point. Please correct me if I'm wrong. Is there any megafunction for fixed point?

    Thanks in advance Tricky.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    There are no megafunctions for fixed point because all of the arithmatic is integer arithmatic. So you either use the standard megafunctions (lpm_mult, lpm_add_sub etc) or you can just use behavioural code.

    This means the latency is MUCH lower, and logic use is MUCH smaller.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Thank you Tricky. I think in my case I need a fractional part which can only be fulfilled by floating point. ie. 0.172212. At my final calculation, my final data range is between -1 to 1.

    Cheers :)
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hi Gunardilin,

    There is nothing to stop you using ordinary integer aritmetic for fractions. I have never used floating point over the course of all projects. You can think of truncation as the decimal point. e.g.

    y * .5 = y * 1024 then chop off 11 bits.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hello kaz,

    Thank you for your reply. I still don't get your idea to use integer arithmatics for fraction. Could you explain further? Thank you in advance.

    Cheers :)
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Fixed point is simply just binary. Imagine the number 9.25

    In 6 bit fixed point:b 1001.01

    This is the same as 37: 100101

    The only difference is a decimal place. So with fixed point arithmatic the decimal point (should probably be called the integer/fraction divider!) is just imaginary, so you would treat the fixed point number as if it was 37.

    The following rules apply:

    An M.N number + X.Y results in a max(M, X)+1.min(N, Y) number.

    M.N * X.Y = M+X.N+Y

    (Where M,N,X,Y are the number of bits).

    Have a look at the VHDL fixed point package:

    www.vhdl.org/fphdl

    Its the 2008 fixed point package in 93 format so you can use it with any synthesisor.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    If you have say a multiplier that has two inputs (signal 12 bits signed and multiplicand 12 bits signed) then you may truncate 12 LSB bits off result.

    That is equivalent to /2^12.

    Thus if your multiplicand is 0.172212 then you first pre-convert it 0.172212*2^12 by hand and round it to 705.

    thus when you truncate 12 LSBs, in effect you multiply by 0.172212

    Thus all you do is scale your mutiplicand from normalised range of (-1 ~ 1)

    by scaling it by 2^12.

    You can additionally do rounding at truncation.

    Edit: additionally you can think of it in your head as fractional value with decimal point somewhere but you don't need to as it is just two ways of looking at same thing.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    With fixed point always remember the range of your values as well and how operators affect them. For example if I had two eight bit fixed point values and I add them together my result is potentially 9 bits. Likewise if I multiplied those two values together I would need 16 bits to store the result.

    So often with high precision fixed point math hardware, if you want to maintain 100% accuracy without rounding through the calculation the logic typically starts off narrow and becomes wider as the data moves through various operators. Then at the end you sometimes truncate the width by downscaling the number. If you round off bits after each operator then keep in mind errors will accumulate.

    I recommend google searching "fixed point math", there are probably plenty of sites that show graphically how you apply it to hardware/software. It'll probably make more sense if you see pictures of it.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Bit growth is inevitable and most practical systems maintain a sort of fixed data path width e.g. 14 or 16 bits commonly between specific modules while allowing full or near full growth inside each module. Naturally that means rounding/occasional saturation. It all can be modelled easily before moving to implementation.