Floating Point and Fixed Point.

Thank you so much for your comments. I have modified it as follows:

Library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

Library altera_mf;

use altera_mf.altera_mf_components.all;

entity floatadd is

port(

inA,inB : in std_logic_vector(31 downto 0);

inclk : in std_logic;

out1 : out std_logic_vector(31 downto 0)

);

end floatadd;

architecture add of floatadd is

begin

fp_add : altfp_add_sub

generic map (

DIRECTION => "ADD",

ROUNDING => "TO_NEAREST",

width_exp => 8,

width_man => 23,

pipeline => 11

)

port map (

clock => inclk,

dataa => inA,

datab => inB,

result => out1

);

end add;

I tried to compile it and it is working. Have to simulate it and check with the results. But is this make senses to you?