Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Floating Point and Fixed Point.

I am beginner in VHDL code. I am currently using Quartus II and wonder if anyone can recommend a good and easy-to-use floating point library? I know there is a megafunction from altera. But, I just w...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago


  signal a : std_logic_vector(31 downto 0);
  signal b : std_logic_vector(31 downto 0);
  signal r : std_logic_vector(31 downto 0);
begin
  fp_add : altfp_add_sub
  generic map (
    DIRECTION => "ADD",
    ROUNDING => "TO_NEAREST",
    width_exp => 8,
    width_man => 23,
    pipeline => 11
  )
  port map (
    aclr => reset,
    clock => clk,
    dataa => a,
    datab => b,
    result => r
  );
The above example uses default values for exponent and mantissa width, of 8 and 23, and has an 11 clock cycle latency by default.