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Altera_Forum's avatar
Altera_Forum
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14 years ago

Flattening Verilog Hierarchy for IP block creation

Guys,

Wonder if someone could point me in the right direction.

I would like to flatten my design hierarchy into 1 file so I can just encrypt that one file for making an IP block. With over 60 files (and include files) a manual process of creating one file is taking ages.

I know that quartus has the VQM writer in but design support was removed for cyclone 3 onwards (I am using a cyclone 3). I am aware of .qxp file and have used it in the past but I don't think it can be encrypted.

Anyone know of anything within Quartus or anything else

I would really appreciate a point in the right direction.

Best Regards

C

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  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I see your point, In my case the IP is tailor made per costumer (and project), so portability is not an issue.

    If we take your more generic (and hence superior) solution, It brings us back to the original post in the thread, how do you automatically encrypt all of your files (assuming multiple files approach).

    I guess it can be done with tcl: run over the qsf, and write a batch file for encryption.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    I've used Altera's AMPcrypt tool for that. you only have to encrypt your top level entity, and then create the .qxp file.

    you'll need to contact Altera directly to get that tool.

    By the way I think I've heard that the new Verilog \ VHDL versions include a built in encryption attribute, but I haven't tried it myself, and I don't know how much Quartus support there is.

    --- Quote End ---

    I'am very interrested to try this tool ("AMPcrypt") but unfortunately i dont't find any informations on Altera's web site.

    Is this tool free ?

    Can you give me a download link or informations ?

    Best regards.