Flattening Verilog Hierarchy for IP block creation

I see your point, In my case the IP is tailor made per costumer (and project), so portability is not an issue.

If we take your more generic (and hence superior) solution, It brings us back to the original post in the thread, how do you automatically encrypt all of your files (assuming multiple files approach).

I guess it can be done with tcl: run over the qsf, and write a batch file for encryption.