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Altera_Forum's avatar
Altera_Forum
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18 years ago

Flash pin placement constraints

I am getting the following errors for a Cyclone III EP3C25F324C8 with QuartusII SP1:

Error: Output or bidirectional pin flash_data[1] in pin location D1 (pad_7) is too close to VREF pin in pin location F3 (pad_8)

Error: Output or bidirectional pin flash_nCE in pin location E2 (pad_9) is too close to VREF pin in pin location F3 (pad_8)

It seems to be suggesting that the dedicated flash pins are too close to Vref. This has confused me because these pins are fixed in the device so I can't move them. I have to use the Vref for this bank because the bank also contains DDR SSTL-2 Class I pins.

This seems to suggest that for this bank you can either use Vref or the flash pins but not both. Is that correct?

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    Hello,

    --- Quote Start ---

    This seems to suggest that for this bank you can either use Vref or the flash pins but not both. Is that correct?

    --- Quote End ---

    Basically yes, I fear. The interesting question is, if Cyclone III active parallel configuration option could coexist with a DDR interface at all. My general impresion is, that active parallel configuaration sounds interesting, but effectively implies so many restrictions, that it may unsuitable for a lot of designs. But I didn't check in detail.

    You should file a SR request to get an official Altera statement in this regard. Furthermore I think, that active parallel interface couldn't disturb VRef during configuration, cause all logic is stopped then. But PFL programmer instance could be active at any time in user mode and could threaten VRef signal integrity.

    Regards,

    Frank