Flash pin placement constraints

Hello,

--- Quote Start ---

This seems to suggest that for this bank you can either use Vref or the flash pins but not both. Is that correct?

--- Quote End ---

Basically yes, I fear. The interesting question is, if Cyclone III active parallel configuration option could coexist with a DDR interface at all. My general impresion is, that active parallel configuaration sounds interesting, but effectively implies so many restrictions, that it may unsuitable for a lot of designs. But I didn't check in detail.

You should file a SR request to get an official Altera statement in this regard. Furthermore I think, that active parallel interface couldn't disturb VRef during configuration, cause all logic is stopped then. But PFL programmer instance could be active at any time in user mode and could threaten VRef signal integrity.

Regards,

Frank