XG_Kang
New Contributor
6 years agoFitter Error
I have a design using 10AX057N4F40E3SG compiled with Quartus Prime Standard 17.1,If I don't change anything just do several compiles, some of the compile results work correctly,som of the compile results don't work. For the error compile results , I find the following strange thing: one signal named 'ram_rd' is connected to the rden port of a dual-port RAM,and at the same ,this signal is also connected to the rdreq port of a FIFO, the RAM and FIFO work in the same clock domain. In SiganlTapII, I can see the signal at the rdreq port of FIFO works(goes to high), and at the same time ,signal at the rden port of RAM keep low. IT is surely a fiiter error. How to fix the problem?