Occasional ContributorFitter Error with Quartus 19.4 and not Quartus 19.1 for HPS_IOPLL_REFCLK_PIN pin location
During migration from Quartus 19.1 to 19.4, I recompile project and fitter error appear.
A clock pin assignment conflict is raising between HPS_IOPLL_REFCLK_PIN and hps_ddr4_pll_ref_clk which is directly connected to pll_ref_clk_clock_sink to drive DDR4 (as describe on screenshot of PlatformDesigner)
Quartus fitter indicates folliwing error :
Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 pin(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (175020): The Fitter cannot place logic pin in region (78, 142) to (78, 143), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The pin name(s): hps_ddr4_pll_ref_clk
Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error (175005): Could not find a location with: HPS_IOPLL_REFCLK_PIN (1 location affected)
Info (175029): AL27
Info (175015): The I/O pad hps_ddr4_pll_ref_clk is constrained to the location PIN_AL27 due to: User Location Constraints (PIN_AL27)
Info (14709): The constrained I/O pad is contained within this pin
Error (15307): Cannot apply project assignments to the design due to illegal or conflicting assignments. Refer to the other messages for corrective action.
How can I solve this error (maybe to connect both clock together ?)
Thx,
