FIR COMPILER II - multiple banks

I am trying to use FIR Compiler II (Quartus II 11.0) to compile a FIR filter. I require two channels and two coefficient banks.

When using the wizard I load the coefficient file with two sets of coefficients, each on its own line. The wizard lets me switch between the one and the other coefficient set, and the pcitures look correct.

When I compile teh scrolling messages says bank count = 2 (or something to that effect). So far so good.

When I look at the VHDL output, however there is no way to switch between the coefficient banks. I expected to see a "BankIn" input signal.

Any ideas?

This is the port definition I get back:

port (

clk : in std_logic := '0'; -- clock_reset.clk

reset_n : in std_logic := '0'; -- clock_reset_reset.reset_n

coeff_in_clk : in std_logic := '0'; -- coeff_clock_reset.clk

coeff_in_areset : in std_logic := '0'; -- coeff_clock_reset_reset.reset

ast_sink_data : in std_logic_vector(13 downto 0) := (others => '0'); -- avalon_streaming_sink.data

ast_sink_ready : out std_logic; -- .ready

ast_sink_valid : in std_logic := '0'; -- .valid

ast_sink_error : in std_logic_vector(1 downto 0) := (others => '0'); -- .error

ast_sink_sop : in std_logic := '0'; -- .startofpacket

ast_sink_eop : in std_logic := '0'; -- .endofpacket

ast_source_data : out std_logic_vector(15 downto 0); -- avalon_streaming_source.data

ast_source_ready : in std_logic := '0'; -- .ready

ast_source_valid : out std_logic; -- .valid

ast_source_error : out std_logic_vector(1 downto 0); -- .error

ast_source_sop : out std_logic; -- .startofpacket

ast_source_eop : out std_logic; -- .endofpacket

ast_source_channel : out std_logic_vector(0 downto 0) -- .channel

);