Finite state machine - doesnt change state second time & glitch

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This is a timed state machine, since my external hardware has timing constraints, so delay_next is set to 10 to ensure that state machine is in that state for 10 clock cycles and then it is allowed to change state to the desired state (in this case idle state).

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Yes, but as you havent included the delay counter on the diagram, you cannot see whether the counter is at 0 yet. Given it has just changed state 5 clocks previous, and needs 10 clocked before changing again, I suspect the counter isnt at 0 yet, hence cannot change state.