Finite state machine - doesnt change state second time & glitch

actually I posted then deleted hastily as I noticed it is clocked.

However, your design is not following a good state machine template in a clean way as you are mixing it with other logic, though I don't think this explains things.

I notice your first observation of tx_bus in write_end state going low then high is actually a glitch of half clock period in first diagram and longer in second diagram. It occurs as state changes from write_end to idle judging by d_state value moving from 100 to 001 (after 10 clocks) and this is expected??

Frankly your design is too complicated to follow on the forum and your description needs further corrections for example tx_bus does go low in init state, idle state and others. The best approach is to simulate it fully before you move to any hardware and repair it accordingly.