Finite state machine - doesnt change state second time & glitch

This is a timed state machine, since my external hardware has timing constraints, so delay_next is set to 10 to ensure that state machine is in that state for 10 clock cycles and then it is allowed to change state to the desired state (in this case idle state).

In the waveform I have attached, it is visible that state machine is in writing_end for 10 clock cycles and then it goes into the idle state. Only when it is again in the idle state, txval goes high but FSM does not go into write_prepare state as it should and as it did in the first case where whole cycle was correctly performed.

I used waveform to test my code since this FSM has only 5 states (one is init) and it has only 1 external stimuli (txval).

Basically, it should be in idle state until for the rising edge of the clock txval is 1. If it is one, it should put txbus to 1 in all states until reaching back into idle. If it reaches idle while txval is still high, it would keep txbus at 1 and go into next writing cycle. This would allow user of this FSM to send only 1 byte or more efficiently a stream of bytes while keeping txval high all the time.

Anyhow, in my waveform testing I am testing for the simple case where FSM user would put data, put txval to high, wait for txbus to go high, put txval to low, wait for txbus to go to low (=back in idle) and then it would put another byte, assert txval again and so on...