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OrF's avatar
OrF
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Find where false_path was set.

Hi, I have a design where there is a physical path between two flip-flops (FF). However, when I try to generate a timing report, the Timing Analyzer shows “nothing to report.” I assume this might be...
Timing
OrF's avatar
OrF
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Hi,

I tried the additional step you suggested, but it still doesn’t resolve the issue. I used the command write_sdc -expand "expanded_sdc.sdc", but the output still includes lines like the following on the false path, and I don’t see it expanding the output delay constraints:

set_false_path -from [get_clocks {rx_*}] -to [get_clocks {pll_*}]
set_output_delay -add_delay -max -clock [get_clocks {tx_clk}] 47.000 [get_ports {DIE0_dib_pad_0_*_*[*]}]
set_output_delay -add_delay -min -clock [get_clocks {tx_clk}] 0.000 [get_ports {DIE0_dib_pad_0_*_*[*]}]

Any further suggestions?

Or.