Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

final procedure block does not work in ModelSim

SystemVerilog LRM (1800-2012):

--- Quote Start ---

A final procedure executes when simulation ends due to an explicit or implicit call to $finish.

--- Quote End ---

But the final block does not execute in ModelSim Altera Starter Edition 10.1e:cry:

I used the following code: 


module test();
initial begin
   # 1 $display("Simulation has been started");
   # 1 $finish;
    end
final
    $display("This should be shown at the end");
endmodule

and this is the output:

# Simulation has been started# ** Note: $finish : C:/.../final_bug.sv(4)# Time: 2 ns Iteration: 0 Instance: /test

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Are you running this code interactively? If so, $finish may be behaving like $stop.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    By "interactively" you mean by using the ModelSim GUI, right?

    By the way did you ever simulate a SystemVerilog code containing a "final block" with ModelSim? if not could you please try it and tell me the results?

    thanks
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Model Technology ModelSim SE qverilog 10.1e Compiler 2013.06 Jun 11 2013
/u/prod/release/10.1e/modeltech/linux/qverilog final1.sv 
-- Compiling module test
Top level modules:
	test
+ /u/release/10.1e/modeltech/linux/vsim -lib work test -c -do run -all; quit -f -appendlog -l qverilog.log -vopt
#  vsim -appendlog -do {run -all; quit -f} -l qverilog.log -lib work -c -vopt test 
#  ** Note: (vsim-3812) Design is being optimized...
#  //  ModelSim SE 10.1e Jun 11 2013 Linux 3.0.13-0.27-default
#  //
#  //  Copyright 1991-2013 Mentor Graphics Corporation
#  //  All Rights Reserved.
#  //
#  //  THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
#  //  WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
#  //  LICENSORS AND IS SUBJECT TO LICENSE TERMS.
#  //
#  Loading sv_std.std
#  Loading work.test(fast)
#  run -all 
#  Simulation has been started
#  ** Note: $finish    : final1.sv(4)
#     Time: 2 ns  Iteration: 0  Instance: /test
#  This should be shown at the end

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Thank You Dave!

    I guess instead of using the GUI, you typed the tcl script and this time the output looks fine.