Model Technology ModelSim SE qverilog 10.1e Compiler 2013.06 Jun 11 2013
/u/prod/release/10.1e/modeltech/linux/qverilog final1.sv
-- Compiling module test
Top level modules:
test
+ /u/release/10.1e/modeltech/linux/vsim -lib work test -c -do run -all; quit -f -appendlog -l qverilog.log -vopt
# vsim -appendlog -do {run -all; quit -f} -l qverilog.log -lib work -c -vopt test
# ** Note: (vsim-3812) Design is being optimized...
# // ModelSim SE 10.1e Jun 11 2013 Linux 3.0.13-0.27-default
# //
# // Copyright 1991-2013 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# //
# Loading sv_std.std
# Loading work.test(fast)
# run -all
# Simulation has been started
# ** Note: $finish : final1.sv(4)
# Time: 2 ns Iteration: 0 Instance: /test
# This should be shown at the end
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