FFT megaCore usage problem

You can capture the output data of the FFT on the positive edge of the clock, there is no problem.

What do you want to do with the output data of the FFT ?

Bc when I capture data at positive edge, it seems to be noise value.. then I observe the value, only values at negative edge are stable values... therefore i wan to capture values at negative edge by designing the negative edge D-flipflop to capture it..

But I need to use signals to enable the D-flipflop... so that it wil capture only the stable value.

You mean that if you put flip-flops to capture the output data of the FFT, the value after the flip-flops are not the same than the value outputed by the FFT ?

Can you put a picture of your simulation, because there is no reason this happen.

I have uploaded the simulation output from the FFT. I have highlighted the noise that occurs (i not sure whether is noise or nt).

Because these random values exist in the simulation output, so i would like to capture value at negative edge of clock

These transitions should not happen, it is not a normal behaviour.

1. Your input data change a little bit after the falling edge of the clock. Why ? They should change on the rising edge of the clock.

2. The source_sop and source_valid signal don't change on a rising edge of the clock, this is not normal. Have you an explanation for this ? The clock signal on the simulation is it well the clock provided to the FFT ?

Moreover it is precised in the avalon interface specifications (§ 6.2.2) that :

--- Quote Start ---

All outputs from a source interface to a sink interface, including the data, channel, and error signals, must be registered on the rising edge of clock.

--- Quote End ---

So everything must be done on the rising edge of the clock.

I am using sine1000Hz as the input to FFT, I used matlab to generate the value for 64 points. However, I am not sure how to give sine1000Hz input to the simulation waveform. Therefore, I keyed in manually the input data, maybe some error during the time I keyed in data. Do you have any advice on how to give an intended input to the simulation file... For instance, sine2000Hz or sine4000Hz or mixed signals beside key in manually?

I also not sure why source_real and source_imag didnt changes at the rising edge of clock...

I provide 100MHz clock frequency to the FFT. Is it too fast for the FFT megaCore? How can I determine the maximum operating frequency of FFT megaCore? Do I check it using TimeQuest Timing analyzer?

Do I need to provide you my vhdl code for reference?

Yes, can you provide your vdhl test bench please, I am not sure to understand how you do it. What did you mean by key in manually ?

Personnaly I also use Matlab to generate the signal I want, and then I copy the values into a std_vector. And in the VHDL I have a counter which is incremented each rising edge of the clock to read each point one after the other.

I know that you can also store the values in file, and read the file from the vHDL, this is more generic, but I never try it.

Maximum frequencies are provided in the FFT user guide, they are far higher than 100 MHz. Anyway, this can cause problem after fitting but not for the simulation, the problem is not here.

In my vhdl file, it consists of a counter, 2 DFF 8 bit, an interface, and the FFT core. but I not sure is this consider testbench? bc I do read some other thread mentioning about testbench which has simulation commands.

But I dont know how to start with the testbench.

I mean key in manually is to set the value one by one in the vector waveform file... Bc I dont know how to make my vhdl code to read data from a file...:(

I think since there is already something wrong with data_real, the problem can come from the waveform you edit or the DFF8 component.

If you want, put the complete project in a zip.

Else about the test bench you have the idea, but maybe you can make simpler. I attach an example of test bench (I didn't try it, it is just to give you the idea of the test bench).

Thanks for the guidance on testbench

I have read the example code you provided, so when I make simulation at modelSim, do I need to include all files in the project to run or just put fft_h.vhd and the test_bench_example.vhd?

Do I need to use the command like

FILE file_in : TEXT is in "data_real.txt";

FILE file_in : TEXT is out "dataout.txt";

VARIABLE line_in : LINE:

VARIABLE line_out : LINE'

VARIABLE input_tmp : INTEGER;

VARIABLE output_tmp : INTEGER;

and command like READLINE()

for declaring the input and output files to provide inputs and obtain output of FFT when using the testbench file you provided?

I notice there is a file fft_h_tb.vhd generated by the FFT megaCore, what is the difference between these 2 files fft_h_tb.vhd and fft_h.vhd?

I also attached the all vhd files of my project. let me know what I should do to improve my vhd coding and integrate the simulation command to them? Thank you.