FFT megaCore usage problem

These transitions should not happen, it is not a normal behaviour.

1. Your input data change a little bit after the falling edge of the clock. Why ? They should change on the rising edge of the clock.

2. The source_sop and source_valid signal don't change on a rising edge of the clock, this is not normal. Have you an explanation for this ? The clock signal on the simulation is it well the clock provided to the FFT ?

Moreover it is precised in the avalon interface specifications (§ 6.2.2) that :

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All outputs from a source interface to a sink interface, including the data, channel, and error signals, must be registered on the rising edge of clock.

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So everything must be done on the rising edge of the clock.