Yes, can you provide your vdhl test bench please, I am not sure to understand how you do it. What did you mean by key in manually ?
Personnaly I also use Matlab to generate the signal I want, and then I copy the values into a std_vector. And in the VHDL I have a counter which is incremented each rising edge of the clock to read each point one after the other.
I know that you can also store the values in file, and read the file from the vHDL, this is more generic, but I never try it.
Maximum frequencies are provided in the FFT user guide, they are far higher than 100 MHz. Anyway, this can cause problem after fitting but not for the simulation, the problem is not here.