FAST_OUTPUT_ENABLE_REGISTER Assigment not recognized

I have to following code which to my understanding should be trivial to be implemented via a fast output enable register. However, the FAST_OUTPUT_ENABLE_REGISTER assignment to the pin is ignored.

entity test_comp is
  port(
     irq : out std_logic;
     ...
  );
end entity;
architecture rtl of test_comp is
  signal irq_assert : std_logic;
begin
  irq <= '0' when irq_assert else 'Z'; -- fast output enable is ignored.
  ...
  process(reset,clk)
  begin
    if reset then
      irq_assert <= '0';
    elsif rising_edge(clk) then
      ...
      if some_condition then
        irq_assert <= '1';
      else
        irq_assert <= '0';
      end if;
      ...
    end if;
  end process;
  ...
end architecture rtl;

entity test_comp is
 port(
  irq : out std_logic;
  ...
  );
end entity;
architecture rtl of test_comp is
  signal irq_assert : std_logic;
  signal irq_level : std_logic; -- must use irq_level somehow or assign syn_keep attribute  to avoid it being removed.
  attribute syn_keep: boolean; 
  attribute syn_keep of irq_level : signal is true;
begin
  irq <= irq_level when irq_assert else 'Z';
  ...
  process(reset,clk)
  begin
    if reset then
    elsif rising_edge(clk) then
      ...
      if some_condition then
        irq_assert <= '1';
      else
        irq_assert <= '0';
      end if;
      ...
    end if;
  end process;
  ...
end architecture rtl;