New Contributor
Super ContributorHi,
PLL IP is missing in the design files. After adding a PLL with expected parameters, the design compiles and also "works" in simulation, when connecting a memory device that replays written data.
I see however several possible problems:
Regards Frank
New ContributorTHnak you for responding. Perhaps I should explain a short history as to what I am trying to achieve. I created a complete PCB and expected it all to work - it did not. Eventually I tracked the fault down to data not being read in from the EEPROM. At that time I used the simple approach of writing to the EEPROM (AT28C64B), set the ouput buffer to tristate and then reading data in as required. This worked fine when I last used Quatus v7.2 fifteen years ago. Since I had to move to version 13.1 I presumed there was a possible problem to using this approach so I added the IO buffers. Still no good. Since I was not sure as to whether the buffer was working correctly or not I added the monitor bus. This proved that the data was written into the EEPROM correctly, and, by holding the FSM in the read state I could see that the correct data was on the EEPROM output pins, the data was correct on the buffers' read in 'pins' but the raeding instance was seeing all highs. This whole little project is to try and trap the cause of the problem. It is stopping me from creating the real project.
Regarding the PLL IP I would assume the megafunction would take care of itself. I do not see what I can do about that. The EEPROM works as it should. The FSM only runs once so that I can 'scope the lines in a steady state. How do I set synchronous reset release? I have enabled the 'DEV_CLRn' if that is any help.
I don't know if any of this helps - I can only hope so.
Regards
Ken
