Forum Discussion
Occasional ContributorFailed to run ip-setup-simulation:
Is this because it is defined in a SystemVerilog package, as mentioned in the user guide?
Does the simulation file generation succeed when you select 'Verilog' instead?
I am not very familiar with the FPGA AI Suite IP, and I believe the default simulation flow may differ when working with it.
I would recommend referring to the user guide below for more details.
https://docs.altera.com/r/docs/863373/2026.1.1/fpga-ai-suite-handbook/the-flow-remove-arch-flow
Regards,
Richard Tan
Occasional ContributorIt seems that it is not possible to generate a simulation for the systems in the example.
Error: altera_ai_ip_2: altera_ai_ip does not support generation for VHDL Simulation. Generation is available for: Quartus Synthesis.
Error: SPD file was not generated: C:\Users\mads\Desktop\agx5_soc_s2m_lt\hw\qsys\ip\dla\dla_altera_ai_ip_2\dla_altera_ai_ip_2.spd
Super ContributorIs this because it is defined in a SystemVerilog package, as mentioned in the user guide?
Does the simulation file generation succeed when you select 'Verilog' instead?
I am not very familiar with the FPGA AI Suite IP, and I believe the default simulation flow may differ when working with it.
I would recommend referring to the user guide below for more details.
https://docs.altera.com/r/docs/863373/2026.1.1/fpga-ai-suite-handbook/the-flow-remove-arch-flow
Regards,
Richard Tan
