New ContributorExternal memory Interface Intel Cyclone 10 FPGA IP configure DATA bus size from Avalon MM interface
I am migrating a system from an old Arria II to a Cyclone 10 GX, so I need to migrate from a DDR2 interface connected to a Avalon MM with an interface of 128 bits.
I would like to use this controller in the Cylone 10 GX Development Kit, so I instanciate the component into my system and I use the Template "Cyclone 10 GX FPGA Development Kit with DDR3" for the Memory parameters.
After that it creates a Avalon MM interface to write/read into the Memory of 320 bits that it is not compatible with a standard Avalon Memory Map Clock Crossing bridge interface (multiple of 2) that my system uses to write and read data.
If I open the example from Altera for this memory the parameters are exactly the same but the Avalon MM interface has 256 bits, so it can be use.
How I can modify this Avalon Interface to be 256 or 128?
Thanks.
Hi ADona,
Cyclone 10 GX package only support DDR3 x40 with ECC. This information cover in “Intel® Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook” page 166.
So, you need to turn on the “Enable Error Detection and Correction Logic with ECC” under the “Controller” setting in order to use DDR3 x40.
Another option is you can use 32 DQ width and you can see now the amm interface become 256bits.
Hope this helps.
Thanks
Regards,
NAli1
