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New ContributorExternal memory Interface Intel Cyclone 10 FPGA IP configure DATA bus size from Avalon MM interface
Hi ADona,
Cyclone 10 GX package only support DDR3 x40 with ECC. This information cover in “Intel® Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook” page 166.
So, you need to turn on the “Enable Error Detection and Correction Logic with ECC” under the “Controller” setting in order to use DDR3 x40.
Another option is you can use 32 DQ width and you can see now the amm interface become 256bits.
Hope this helps.
Thanks
Regards,
NAli1
Frequent ContributorHi ADona,
The Avalon MM interface setting is actually depend on the DQ width setting and the clock rate of user logic set by user. To get better clue on how to get the Avalon interface setting, please refer to below examples. Assuming the DQ width is equal to 64.
Example 1:
DQ width = 64
Clock rate of user logic = Half
Avalon MM interface = DQ width x Clock rate of user logic
= 64 x 2 = 128 bits
Example 2:
DQ width = 64
Clock rate of user logic = Quarter
Avalon MM interface = DQ width x Clock rate of user logic
= 64 x 4 = 256 bits
I sincerely hope this helps.
Thanks
Regards,
NAli1
TFPGAThanks Nali1,
The problem is that my DQ is 40, and this data cant be modified because the external memory has a dataline of 40 bits (Cyclone 10 GX FPGA Development Kit).
And the Avalon bridge only accept multiple of 2 data witdh.
Error: core.ddr3.ctrl_amm_0: Data width must be of power of two and between 8 and 4096
Regards,
ADona
